In order to enhance avalanche capability, clamp diodes are formed between Gate and Drain for MOSFET and between Gate and Collector for IGBT, respectively. However, breakdown voltage degradation in main devices may be introduced while forming this integrated configuration in prior art if the clamp diodes are made on a polysilicon layer placed across the edge termination. The interaction between the electric fields in the polysilicon clamp diodes and edge termination may significantly degrade breakdown voltage of the main devices.
FIG. 1 is a circuit diagram of a MOSFET with gate-drain clamp diodes and FIG. 2 is the cross section view of a MOSFET of prior art (U.S. Pat. No. 5,631,187) where the cell is formed on N substrate 200. On the top surface of the substrate 200, there is an N+ source region 210 surrounded by a P body region 211. A metal layer 220 makes electrical contact to both said N+ source region 210 and P body region 211 acting as a source electrode. Meanwhile, metal layer 222 and 221 are deposited to function as a gate electrode and a drain electrode of the cell structure, respectively. Between the gate electrode and drain electrode, a serial of back-to-back polysilicon diodes 230 are formed across over the termination to enhance the avalanche capability of the semiconductor power device.
The prior art discussed above is encountering a technical difficulty which is that, as the gate-drain (or gate-collector for IGBT) clamp diode crosses over termination, a problem of breakdown voltage degradation will be arisen due to electric field in termination region is blocked by polysilicon.
Accordingly, it would be desirable to provide a new and improved device configuration to prevent the degradation of breakdown voltage from happening.